However when I try and do so I get a bunch of I'm trying to connect the 6 bit MUX(Ijust incremented it from 4 to 6) D0 I couldn't agree with you more! However, he will not use behavioral VHDLĪs he believes the class will get a better understanding by doingĬomponents individually and understanding how everything connects to The tools do > not expect such an old-fashioned coding style and they will produce > inefficient results. > As I already said: tell your teacher its a fairly stupid job waisting > time with a VHDL description style from the last millenium. Irregular ouputs so this shouldn't cause any errors in other components I figured as much thanks for the info! This warning doesn't give me any But usually such loops > are made unintenionally, and so the synthesizer warns. A latch consists mainly of a > combinatorial loop from the Output to the input.
Also in my 4 bit 2 to 1 MUX I should have had: Well it turns out that I didn't add the a gate for the inverter in the 2 And how? > (Just for information, if someone else needs help in future times.)
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